CLKEN=0, PIXSEL=0, CLKSEL=0
System Control Block Version and Panel Clock Control Register
| DCDR | Clock division ratio setting controlRefer toTable 2.7.1 for details about setting value.Note: Settings that are not listed in table 2.7.1 are prohibited. |
| CLKEN | Panel clock output enable controlNote: Before changing the PIXSEL,CLKSEL or DCDR bit, this bit must be set to 0. 0 (0): Disable panel clock output 1 (1): Enable panel clock output |
| CLKSEL | Panel clock supply source select 0 (0): External clock select 1 (1): PLL output select |
| PIXSEL | Pixel clock select control.Must be set to the same value as OUT_SET.FRQSEL[1]. 0 (0): No frequency division, parallel RGB 1 (1): Quarter frequency,serial RGB |
| VER | Version informationVersion information of the GLCD |